1. Field of the Invention
The present invention relates to a MOS type semiconductor device having a lightly doped drain (LDD) structure.
2. Description of the Related Art
For a so-called submicron class MOS transistor having a gate length below 1 .mu.m, the LDD structure reducing electric field concentration near the drain is used for the purpose of preventing degrading of characteristics of the transistor due to injection of hot carriers into a gate oxide film or a bottom part of sidewall by the electric field concentration near the drain.
In a conventional MOS type transistor having the LDD structure, as disclosed, for example, in JP-A-62-290176 (1987) and JP-A-2-117176 (1990), the gate oxide film serving as a dielectric field is formed on a p-conductivity type semiconductor silicon substrate and a gate electrode made of a conductive film such as a polycrystalline silicon film, a transition metal film or a composite film thereof is formed thereon. In the case where a polycrystalline silicon film is used for the gate electrode, impurities such as phosphor and boron are diffused therein in order to reduce the resistance thereof.
Low impurity concentration diffusion layers (n-type layers) are formed in the p-conductivity type semiconductor silicon substrate by injecting by the ion implantation method and diffusing n-conductivity type impurities in portions, where source and drain regions are to be formed, by using the gate electrode as a self-alignment mask.
Then sidewall spacers are formed on both sides of the gate electrode using a film of an insulating material such as silicon dioxide, and high impurity concentration layers (n.sup.+ type layers) serving as source and drain regions are formed by injecting by the ion implantation method and diffusing n-conductivity type impurities in portions of the low impurity concentration diffusion layers described above, other than the portions located below the sidewall spacers by using these sidewall spacers as a self-alignment mask.
As described above, in a MOS type semiconductor device having an LDD structure, since the low impurity concentration diffusion layers are formed in the portions of the source and drain regions just below the sidewall spacers, electric field concentration is reduced in these portions.
However, in a conventional MOS type semiconductor device having the LDD structure, use of sidewall spacers made of an insulating film creates a problem since the low impurity concentration layers just below these sidewall spacers act as parasitic resistance between the MOS channel and the high impurity concentration diffusion regions, resulting in degrading conductance characteristics of the transistor.